Scan testing of circuits is accomplished by connecting scan elements (e.g., latches) in series in a test path. The output of each scan element is fed to an input of a next scan element in a scan chain. Faults resulting from manufacturing defects can cause timing related errors in the test path. Faults that reflect interdependencies of scan elements can prevent certain data paths from being executed. The unexecuted paths can prevent failing locations from being detected, diagnosed and corrected. Diagnosing failing locations can lead to fabrication process and design changes to improve later yield and reduce waste.